1. Field of the Invention
The present invention pertains to the field of computer graphics systems. More particularly, this invention relates to a frame buffer system with non overlapping pixel buffer access, variable interleaving, nibble replication and unaligned VRAM/DRAM memory access.
2. Art Background
Prior computer graphics systems typically include a graphics subsystem that receives graphics data from a host processor and renders images defined by the graphics data onto a display. A typical prior graphics subsystem comprises a rendering controller or rendering processor, a frame buffer, a frame buffer post processor, and a digital to analog converter (DAC).
The rendering controller in such a prior system usually receives the graphics data from the host processor over a system bus. The rendering controller generates a set of pixel data according to the graphics data from the host processor. The rendering controller then writes the pixel data into the frame buffer.
The frame buffer in such a system typically contains a set of video random access memories (VRAMs) that buffer the pixel data generated by the rendering controller. Prior high performance graphics subsystems usually implement frame buffers with multiple interleave factors. Such multiple interleave frame buffers improve pixel data throughput between the rendering controller and the VRAMs. A multiple interleaved frame buffer overcomes the input/output bandwidth limitations of conventional VRAMs.
In such a prior system, the frame buffer typically transfers the pixel data to the frame buffer post processor over a pixel bus. The frame buffer post processor typically generates video data corresponding to the pixel data by performing frame buffer post processing functions on the pixel data. The frame buffer post processing functions typically include color look-up table functions and cursor control functions.
The frame buffer post processor typically transfers the video data to the DAC over a video bus. The DAC then performs digital to analog conversion functions on the video data and generates a set of analog video signals for the display device. The analog video signals typically include the red, green, and blue video signals and video sync signals for generating a display on the display device.
Such a multiple interleave frame buffer usually transfers multiple pixel data values in parallel over the pixel bus to the frame buffer post processor. Such a parallel transfer of multiple pixel data values requires that the frame buffer post processor provide a large number of input/output pins to accommodate the parallel pixel data.
For example, a common prior multiple interleave frame buffer provides a five way interleave factor. Such a frame buffer transfers five pixel data values in parallel over the pixel bus. Each pixel data value transferred over the pixel bus typically comprises 32 bits for a high resolution display device. As a consequence, the frame buffer post processor must provide 5.times.32 input pins for accepting the pixel data over the pixel bus. Unfortunately, such a high number of input pins greatly increases the manufacturing cost of the frame buffer post processor.
Furthermore, such a multiple interleave frame buffer usually transfers video data for multiple pixels in parallel over the video bus to the DAC according to the interleave factor of the frame buffer. Such a parallel transfer of video data also increases the number of output pins (5.times.24) for the frame buffer post processor, thereby increasing frame buffer post processor manufacturing costs. Such increased manufacturing costs of the frame buffer post processor greatly increases the overall system computer graphics system cost.
In addition, prior computer graphics systems commonly provide a frame buffer that accommodates 24 bit values in either single buffered or double buffered mode. Each 24 bit value usually provides a 24 bit pixel data value in single buffered mode, or a pair of 12 bit double buffered pixel data values in double buffered mode. Each 24 bit pixel data value typically comprises an 8 bit red value, an 8 bit green value, and an 8 bit blue value. On the other hand, each 12 bit double buffered pixel data value comprises a 4 bit red value, a 4 bit green value, and a 4 bit blue value in a double buffered arrangement.
In such a system, the frame buffer post processor typically implements separate color look-up tables for 24 bit single buffered and the 12 bit double buffered modes. Such a prior system typically provides color look-up tables with 256 colors for the 24 bit buffer single buffered mode and color look-up tables with 16 colors for the 12 bit double buffered mode. Unfortunately, the additional color look-up tables for the 12 bit double buffer mode increases the cost of the frame buffer post processor. Such increased cost contributes to increased costs of the overall computer graphics system.